The present invention relates generally to packet switching devices employed in multi-processor and parallel computer systems, and digital communications equipment, and the like, and more particularly to packet switching devices which utilize pluralities of queue sets individually coupled to the input ports thereof which are employed to sort and store data packets in order to reduce output port contention between data packets arriving at the same input port.
One developing area of computer technology involves the design and development of large-scale, multi-processor-based distributed and parallel computer systems. Typical of these classes of computer systems and architectural approaches are the single instruction stream, multiple data stream (SIMD) computer architecture and the multiple instruction stream, multiple data stream (MIMD) computer architecture.
A SIMD computer typically comprises a control unit, N processors, N memory modules and an interconnection network. The control unit broadcasts instructions to all of the processors, and all active processors execute the same instruction at the same time. Each active processor executes the instruction on data in its own associated memory module. The interconnection network provides a communications facility for the processors and memory modules.
A MIMD computer typically comprises N processors and N memories, and each processor can execute an independent instruction stream. Each of the processors may communicate to any other processor. Similar interconnection networks may be employed in the MIMD computer.
Various interconnection networks may be employed to interconnect processors and memories employed in either type of computer system. These interconnection networks include delta networks, omega networks, indirect binary n-cube networks, flip networks, cube networks and banyan networks, for example.
The above-cited networks are discussed in some detail in the following publications: "LSI implementation of modular interconnection networks for MIMD machines," 1980 Int'l. Conf. Parallel Processing, Aug. 1980, pp. 161-162; "Analysis and simulation of buffered delta networks," IEEE Trans. Computers, Vol. C-30, pp. 273-282, April 1981; "Processor-memory interconnections for multiprocessors," 6th Annual Int'l. Symp. Computer Architecture, April 1979, pp. 168-177; "Design and implementation of the banyan interconnection network in TRAC," AFIPS 1980 Nat'l. Computer Conf., June 1980, pp. 643-653; "The multistage cube: a versatile interconnection network," Computer, Vol. 14, pp. 65-76, Dec. 1981; "The hybrid cube network," Distributed Data Acquisition, Computing and Control Symp., Dec. 1980, pp. 11-22; and "Performance and implementation of 4.times.4 switching nodes in an interconnection network for PASM," 1981 Int'l Conf. on Parallel Processing, Aug. 1981, pp. 229-233.
Several types of data switching techniques may be employed to transfer data in SIMD and MIMD computers, and the like, including packet switching, message switching, time-division circuit switching or space-division circuit switching. Packet switching involves sending one or more words of data at time through the system.
Conventional packet switching interconnection networks have a well-known problem involving the speed of transmission of information through the network. Conventional designs have typically employed a single queue coupled to each input port of the network to store and forward data packets to all the output ports. In the single queue system, a contention problem occurs due to the fact that a data packet destined for output port 2, for example, is blocked from exiting through that port because a data packet destined for output port 1 is physically ahead of it in the queue and has not yet exited through port 1. This contention problem causes unnecessary delays in system throughput.
One packet switching node design that attempts to alleviate this problem is disclosed in the article "The hybrid cube network," cited above. The network of interest is shown in FIG. VI.2 on page 12. This Figure shows a switch node comprising two input ports, each of which is coupled through separate queue selection logic to two queues, identified as straight and exchange. The outputs of the two queues of each pair of queues is coupled through queue selection and switch logic to two output ports.
A straight/exchange signal is included in the data packets processed by the circuit which allows the packets to be gated directly into the appropriate queue during the transfer cycle. The data packets are gated through the second queue selector and switch to the appropriate output port by control logic in the control section. It is stated that a 4 to 1 multiplexer could be employed in place of the second queue selector and switch in order to gate the data packets to the appropriate output port.
The operation of this switch node is somewhat similar to the operation of the present invention. However, as is discussed hereinbelow, the structure and operation of the present invention is different than this switch node. A principal difference between the straight/exchange switch node and the present invention is that the former connects any queue output to any output port and, as will be disclosed below, the latter connects each queue output to exactly one output.